fpga and verilog

1.language for hardware --- http://iverilog.wikia.com/wiki/Simulation
2.operating system ----- http://www.drdobbs.com/blog/archives/2010/06/inexpensive_fpg.html;jsessionid=HHOOB0RLEB2XLQE1GHOSKH4ATMY32JVN
3.future is using systemC for synthesis of phy
4.http://www.edaboard.com/thread68357.html --- basic level wimax phy/mac

5.Before implementing a radio phy
decide using
matlab + dsp + pcb radio
systemC + fpga + pcb radio
verilog + fpga + pcb radio

6.TASK is to find minimal requirement to test
3rd party lte phy against -------------- one item in 5
7.C and MATLAB are languages



8.
systemC
| |
| synthesis-----mentorgraphics
|
-------simulation----modelsim
9.one APPROACH

download wimax phy code from hack site
its in systemC
use the above conversion model

10.TI tranceiver
http://docs.google.com/viewer?a=v&q=cache:kS_vtFHnmXoJ:focus.ti.com/general/docs/lit/getliterature.tsp%3FliteratureNumber%3Dslwu045%26fileType%3Dpdf+TI+dsp+kit+for+wimax+testing&hl=en&gl=in&pid=bl&srcid=ADGEESi3KhqXSbtILjhIRHJf6mn8I0jDyPRHOIuSIPSoIdjpXLJeBlb32MAy7bQF_jyfGaHDyxYsK7LGhxtPOjaUIupoVQ6W-VQ4ePIJhGLrvR_Uq_TTDpqFsaznpOszKccfk7GhmGbp&sig=AHIEtbR9No5uMxON8fylSqynDhJOqibhJw

arm cache and memory barrier

1.The main issue
compiler by default orders the instructions
optimizations may further reorder them
once the instructions get loaded into L1/L2 cache,then its rearranged by the core before
feeding into the cpu...here is where barrier comes into picture

A C code line should be converted to assembly,before we can decide whether we need to
use some kind of barrier or not

1.http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka14041.html
2.Memory barrier detailed
http://www.mjmwired.net/kernel/Documentation/memory-barriers.txt

MESI,MSI

MSI - modified,shared,invalid state of cache protocol

Cache Invalidation and Flushing
The VIRTUAL address is the argument for invalidation and flushing

wbinvd ---- writes cache back to memory and marks it empty
invd ---- just marks the cache as invalid without writing to ram

Excellent optimization tip
http://www.agner.org/optimize/

dma cache coherency

1.while a cpu has updated a buffer and about to give control and dma is about to start to device,
another cpu may update the same variable ... dma stales
2.after device dma's buffer, one cpu writes a variable to same buffer and another cpu reads it ...again its stale


1.cache invalidation and cache flushing are complementaries
2.Assume a copy of variable is read into cache
cpu modifies the cache value
but the ram value is old
if at this time device reads the variable(dma writes to device)
device sees incorrect value

3.Again a variable is reflected in cache
device updates the value in ram of variable
but cpu reads the stale value from cache

http://msdn.microsoft.com/en-us/library/ff545924(VS.85).aspx

===========================
1.above dma coherence simple scenario
2.cache line dma coherence scenario

scenario 2 explained
device writes to ram for a variable x
vaiable shares a cache line with another variable y
cpu modifies the variable y and flushes y
stale value of x is also flushed
it overwrites x in ram
later wrong value of x is read into cache and by cpu

another one
system is about to write x to device
another thread cpu modifies x
system will write old value

dma and intr

1.dma needs specially reserved ram block(real physical pages)
2.dma needs virtual physical pages ie a block of physical addresses that is not mapped to ram
3.cpu write-->cache-->dma phy addr-->hardware
4.dma read-->dma phy addr-->cache-->cpu read
5.if cache line is shared by dma buffer and cpu buffer
copy dma part to phy buffer
cpu write new data to dma part
cpu invalidates cpu buffer
dma part data is over written in phy buffer
phy buffer is dma'ed

hw dma reads to phy buffer
cpu writes to cpu buffer
invalidation writes stale dma part to phy buffer,data overwritten
cpu reads the dma phy buffer ,finds old value


================

1.irq save , saves the current cpus all interrupt flags(or current drivers interrupt?) and
disables "this or all" interrupt on current cpu, also takes the spinlock raw variable
1.1 other cpu gets this interrupt, but spins on the spinlock hence, interrupt waits

2.if the same was done using semaphore, interrupts are not disabled , function takes the semaphore,
an interrupt comes on the same cpu,calls the same function,reaccquires the semaphore and deadlock,because previous invokation has to run on the same cpu

3.from timer irq save is not required since local cpu interrupt is disabled

4.

multithreads

1.
thread1:
add to list
increment

thread2
add to list
increment

if the requirement is thread muxing ie 2 threads --> 1 thread processing
best implementation is
lock
add to list
if( increment ) {
release
}
else {
release
}
otherwise at cpu register level there should be an atomic xchange like cmd

any two register values modified complete state cannot be determined using single register

on the processing side ,with the above construct one variable can determine state
since incr and addlist is done atomic

========================
main process and deinit

deinit:
set flag
check if process increment flag is 0 else loop
proceed

process:
if flag do nothing
else carry on

project execution

1.Need 5 or more teams with min 2 resources
2.sliding window method of project execution
ie at any point of time in the project execution phase 1 of the 5 teams will be in focus
the subsideries will do codebuild up or unilevel testing
the window will rotate over the teams
and a release will be reached

======================
1.successful project
1.1 team skill set
1.2 number of human resources
1.3 number of non-human resources
1.4 task breakup and distribution
1.5 tracking progress