wince dma

0.http://blog.csdn.net/hugohong/archive/2009/05/28/4222880.aspx
1.http://support.microsoft.com/kb/299355
2.http://groups.google.com/group/microsoft.public.windowsce.platbuilder/browse_frm/thread/90975e5dd0887119/1e5539324ae5ad71?lnk=st&q&rnum=40&pli=1
3.cache routines in ce
http://msdn.microsoft.com/en-us/library/ms901761.aspx
4.http://us.generation-nt.com/arm-cache-flush-cache-invalidate-help-65004682.html
5.http://www.tech-archive.net/Archive/WindowsCE/microsoft.public.windowsce.embedded/2004-05/0175.html

software development - what can go wrong

1.redundencies - essential data structures are repeated at many places.But sometimes it becomes necessary to keep redundency for eg in protocol development an upper layer will need to maintain the states of the lower layer.The idea here is not optimization but necessity to physically isolate a layer that can even go into hardware from software space.
2.Incomplete understanding of system environment in which the software runs.for eg
multithreaded nature of entry points,semantics of the return values of entry points,presumption of a concept to be same as a similar one.eg tdi interface works only in synchronous mode,trying to use it as async.
3.function redundencies
4.trying to create monolithic design,need to create binaries that work together,clearly separated interfaces and datastructures
5.not caring about the dont do's of sw development
6.non focussed approach
7.not having roadmap
8.not packaging
9.not having test cases

top down and bottom up development

1.Top down - within a period of time, minimal demoable product is made.After each successive period more and more features is added.So at each interval demoable
product is present.Progress is measurable at each interval.Design changes doesnt waste effort too much.

2.Bottom up - First demoable product takes time.multiple units work parallelly to
develop all the features.Integration and testing takes time.After the first stage things will be fast.The design has to be perfect from start otherwise the work done
will be void.

3.For TD approach, first interval will have the framework ready with few features.
Rest of the system development will fall into placeholders of the framework.

4.For time estimation - When deciding to add a feature or modify a feature,find how many .c files .h files will be affected,how many functions will be affected, if it
spans across 5 files and 5 functions it will defenitely take 1 day cycle of modification,review,testing.If its a new feature addition again idea has to be gathered for its imapact on the number of .c and .h files and code addition,review,testing cycle,again for (5,5) it will take around 2 days(because of white space filling code addition).

5.types of modification - no data structure addition/deletion with code changes,data structure addition/deletion with code changes

binder req

1.any process should be able to transfer control and data to any other process in the system
2.device driver is equally visible to all processes in the system
3.a mechanism that can uniquely package data and control from one process to another
4.process A wants to send data and control,it sends ioctl to b-driver,telling which process to send,which function to call,which data to process.
5.b-driver has a mechanism where it can find from the given information the target process where its target entry points are present,it invokes the target process,passes control to the entry point with data.
6.passing control to the entry point-- at initialization in source and target, an ioctl, a thread is kept waiting for a notification or even APC is defined in the process.Once b-driver determines its target it calls the process through returning the ioctl,waking thread,or calling apc with the
entry points control code.it also passes data to the target.

android opencore

1.platform-->MIO-->encoder(-->hwaccelerator)-->controller
-->decoder(-->hwaccelerator)-->MIO-->platform
2.application-->player-->parser-->controller

catergories in sw-hw development

1.pure s/w - cost a pc ~ ~20kR --- ibm
2.firmware - cost a development kit with single DSP~ 20kR to 30kR - TI
3.verilog/systemC - cost a FPGA - 2LkR - Xilinx
4.verilog/systemC - cost a SDR FPGA with multi-DSP - 4LkR - Lyrtech + TI

1.FPGA - an arrangement of various IP cores
product will be one single component
for eg: LTE on fpga,
phy will be from X
i2c/spi from Y
pcie from Z
only NAS to MAC will be developed by current company

sometimes the vendor may give some of the above or it needs to be bought from 3rd party

way to align for big projects

1.think of framework,maintanace and module teams
2.framework team can be 3 to 10
3.maintenance can be 3-5
4.module can be around 5
5.all 3 working parallely from day 1
6.Main issues is development branching and merging
7.it can also be that during initial stages people are aligned for framework and later moved into others
8.highest indicators of the resources are interfaces and the number of entry points,independent libraries and overall framework
9.critical design components are innate scheduling and memory ownership
10.a library if having the property of changing , there should be 2 teams following it.core and maintanace,
11.the fundamental principle being even if 1 line of code is chaged per day , if its known what is to be changed, the goal will be achieved
12.the framework team has to be ahead than others all time, first deliverable from them
13.maintanance team goal is to achieve uniformity,symmetry everywhere also to bring up gaps
14.module teams have to follow the framework team close