dma and intr

1.dma needs specially reserved ram block(real physical pages)
2.dma needs virtual physical pages ie a block of physical addresses that is not mapped to ram
3.cpu write-->cache-->dma phy addr-->hardware
4.dma read-->dma phy addr-->cache-->cpu read
5.if cache line is shared by dma buffer and cpu buffer
copy dma part to phy buffer
cpu write new data to dma part
cpu invalidates cpu buffer
dma part data is over written in phy buffer
phy buffer is dma'ed

hw dma reads to phy buffer
cpu writes to cpu buffer
invalidation writes stale dma part to phy buffer,data overwritten
cpu reads the dma phy buffer ,finds old value


================

1.irq save , saves the current cpus all interrupt flags(or current drivers interrupt?) and
disables "this or all" interrupt on current cpu, also takes the spinlock raw variable
1.1 other cpu gets this interrupt, but spins on the spinlock hence, interrupt waits

2.if the same was done using semaphore, interrupts are not disabled , function takes the semaphore,
an interrupt comes on the same cpu,calls the same function,reaccquires the semaphore and deadlock,because previous invokation has to run on the same cpu

3.from timer irq save is not required since local cpu interrupt is disabled

4.

multithreads

1.
thread1:
add to list
increment

thread2
add to list
increment

if the requirement is thread muxing ie 2 threads --> 1 thread processing
best implementation is
lock
add to list
if( increment ) {
release
}
else {
release
}
otherwise at cpu register level there should be an atomic xchange like cmd

any two register values modified complete state cannot be determined using single register

on the processing side ,with the above construct one variable can determine state
since incr and addlist is done atomic

========================
main process and deinit

deinit:
set flag
check if process increment flag is 0 else loop
proceed

process:
if flag do nothing
else carry on

project execution

1.Need 5 or more teams with min 2 resources
2.sliding window method of project execution
ie at any point of time in the project execution phase 1 of the 5 teams will be in focus
the subsideries will do codebuild up or unilevel testing
the window will rotate over the teams
and a release will be reached

======================
1.successful project
1.1 team skill set
1.2 number of human resources
1.3 number of non-human resources
1.4 task breakup and distribution
1.5 tracking progress