eclipse short cut,commands

1.http://dmy999.com/article/29/using-eclipse-efficiently
2.http://sandarenu.blogspot.com/2008/02/using-bookmarks-in-eclipse.html
3.
ctrl+pgup/pgdown toggle open files
alt+d,alt+s --bookmark

=============
1.find . -name \*.ko -print0 | xargs -0 rm

A/V receiver mania

1.Package
Onkyo TX-NR808 7.2 receiver
+Boston Acoustics SoundWare XS 5.1 speakers
+netgear client/server wireless router
using netgear as a wireless repeater --- http://kb.netgear.com/app/answers/detail/a_id/77
OR WPN802 rangemax

memory barriers: more

1.there is a control logic outside pipeline of all the cpus that determines which instruction and
data blocks go where

2.sequence of instructions on one cpu does not follow any ordering(weakest ordering)
even if there are barrier commands ,the same cpu will still see random ordering
but some possibilities will be restricted in special sequences

3.The barrier in a sequence of instructions in a cpu will make sense with a complementary barrier in
another cpu.

4.best way to picture barrier operations is:
imagine,
one cpu
a sequence of instructions
imagine a output pipeline that contains the result of the above sequence
pipeline is a queue,and the front of the queue will be committed to memory first

we can see that the pipeline can contain a permutation of the sequence of instructions

also when analysing the pipeline remember that the sequence in the pipeline is as seen by another cpu

ie at any execution point in the cpu2(its pipeline) any element in cpu1 pipeline can be assumed to be the current point.

1.smart-fetch strategy dma cache
http://www.usenix.org/event/nsdi09/tech/full_papers/tan/tan_html/index.html

Understanding memory barriers

http://www.mjmwired.net/kernel/Documentation/memory-barriers.txt

1.fix the model
for single cpu
cpu-->data cache-->multiple instr cache--->controller--->memory
cpu-->multiple data cache-->multiple instr cache--->controller--->memory

2.
cpu1 cpu2
stmt 1;
stmt 2;
O[ ]
I[ ]
stmt 3;
stmt 4;

the analysis of memory barriers use will be based on
values of variables at "O" and "I"

At beginning of analysis,assume ctrl is at stmt4
then evaluate values of ALL variables at "O" and "I"
combine with stmt4 or stmt5 the above results

A barrier may come between stmt1 and stmt2 also stmt3 and stmt4
combine above analysis in the context of barriers