memory barriers: more

1.there is a control logic outside pipeline of all the cpus that determines which instruction and
data blocks go where

2.sequence of instructions on one cpu does not follow any ordering(weakest ordering)
even if there are barrier commands ,the same cpu will still see random ordering
but some possibilities will be restricted in special sequences

3.The barrier in a sequence of instructions in a cpu will make sense with a complementary barrier in
another cpu.

4.best way to picture barrier operations is:
imagine,
one cpu
a sequence of instructions
imagine a output pipeline that contains the result of the above sequence
pipeline is a queue,and the front of the queue will be committed to memory first

we can see that the pipeline can contain a permutation of the sequence of instructions

also when analysing the pipeline remember that the sequence in the pipeline is as seen by another cpu

ie at any execution point in the cpu2(its pipeline) any element in cpu1 pipeline can be assumed to be the current point.

1.smart-fetch strategy dma cache
http://www.usenix.org/event/nsdi09/tech/full_papers/tan/tan_html/index.html