Understanding memory barriers

http://www.mjmwired.net/kernel/Documentation/memory-barriers.txt

1.fix the model
for single cpu
cpu-->data cache-->multiple instr cache--->controller--->memory
cpu-->multiple data cache-->multiple instr cache--->controller--->memory

2.
cpu1 cpu2
stmt 1;
stmt 2;
O[ ]
I[ ]
stmt 3;
stmt 4;

the analysis of memory barriers use will be based on
values of variables at "O" and "I"

At beginning of analysis,assume ctrl is at stmt4
then evaluate values of ALL variables at "O" and "I"
combine with stmt4 or stmt5 the above results

A barrier may come between stmt1 and stmt2 also stmt3 and stmt4
combine above analysis in the context of barriers