memory barrier

In SMP cpus sync with each other using MESI protocol

suppose a drivers buffer and a variable is declared side by side in its control block

ie

struct device {

char a;
char buff[x];
};

Unfortunately if the variable and the buffer happen to share same cache line , problems can arise

see the sequence
1.Dma writes to the buffer with shared cache line
2.user thread writes to the variable with shared cacheline
3.please note that the cpu handling dma write after process and the cpu associated with thread
might be different
4.so if the dma write after processing happens first and variable write after processing happends next the original dma content will be overwritten by the variable write