memory barriers

smp systems have multiple processors
each processor has a cache
a cache can have multiple banks (odd and even)

a cache is a hash table
4 bit table with 2 entries -- total 16 + 16 entires -- both code and data lines
bit 8-11 are used a lines rest 8 bits form the cache line

on a dual processor system 2 threads are executing each one one proc,both accessing the flag
if one proc writes to the flag, behind the scene the value needs to be taken from the cache,moved
through the cache interconnect to the memory and again the interconnect need to update the cache of the second processor