dma cache coherency

1.while a cpu has updated a buffer and about to give control and dma is about to start to device,
another cpu may update the same variable ... dma stales
2.after device dma's buffer, one cpu writes a variable to same buffer and another cpu reads it ...again its stale


1.cache invalidation and cache flushing are complementaries
2.Assume a copy of variable is read into cache
cpu modifies the cache value
but the ram value is old
if at this time device reads the variable(dma writes to device)
device sees incorrect value

3.Again a variable is reflected in cache
device updates the value in ram of variable
but cpu reads the stale value from cache

http://msdn.microsoft.com/en-us/library/ff545924(VS.85).aspx

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1.above dma coherence simple scenario
2.cache line dma coherence scenario

scenario 2 explained
device writes to ram for a variable x
vaiable shares a cache line with another variable y
cpu modifies the variable y and flushes y
stale value of x is also flushed
it overwrites x in ram
later wrong value of x is read into cache and by cpu

another one
system is about to write x to device
another thread cpu modifies x
system will write old value