memory barriers: more

1.there is a control logic outside pipeline of all the cpus that determines which instruction and
data blocks go where

2.sequence of instructions on one cpu does not follow any ordering(weakest ordering)
even if there are barrier commands ,the same cpu will still see random ordering
but some possibilities will be restricted in special sequences

3.The barrier in a sequence of instructions in a cpu will make sense with a complementary barrier in
another cpu.

4.best way to picture barrier operations is:
imagine,
one cpu
a sequence of instructions
imagine a output pipeline that contains the result of the above sequence
pipeline is a queue,and the front of the queue will be committed to memory first

we can see that the pipeline can contain a permutation of the sequence of instructions

also when analysing the pipeline remember that the sequence in the pipeline is as seen by another cpu

ie at any execution point in the cpu2(its pipeline) any element in cpu1 pipeline can be assumed to be the current point.

1.smart-fetch strategy dma cache
http://www.usenix.org/event/nsdi09/tech/full_papers/tan/tan_html/index.html

Understanding memory barriers

http://www.mjmwired.net/kernel/Documentation/memory-barriers.txt

1.fix the model
for single cpu
cpu-->data cache-->multiple instr cache--->controller--->memory
cpu-->multiple data cache-->multiple instr cache--->controller--->memory

2.
cpu1 cpu2
stmt 1;
stmt 2;
O[ ]
I[ ]
stmt 3;
stmt 4;

the analysis of memory barriers use will be based on
values of variables at "O" and "I"

At beginning of analysis,assume ctrl is at stmt4
then evaluate values of ALL variables at "O" and "I"
combine with stmt4 or stmt5 the above results

A barrier may come between stmt1 and stmt2 also stmt3 and stmt4
combine above analysis in the context of barriers

Maybe FL studio first

http://www.youtube.com/watch?v=JGttxDgo6jc&feature=related
1.wish list: power jack in car
M studio : min keys midi controller
midi out to car speakers
2.http://www.youtube.com/watch?v=CHL95HSXHbE&feature=fvw

fpga and verilog

1.language for hardware --- http://iverilog.wikia.com/wiki/Simulation
2.operating system ----- http://www.drdobbs.com/blog/archives/2010/06/inexpensive_fpg.html;jsessionid=HHOOB0RLEB2XLQE1GHOSKH4ATMY32JVN
3.future is using systemC for synthesis of phy
4.http://www.edaboard.com/thread68357.html --- basic level wimax phy/mac

5.Before implementing a radio phy
decide using
matlab + dsp + pcb radio
systemC + fpga + pcb radio
verilog + fpga + pcb radio

6.TASK is to find minimal requirement to test
3rd party lte phy against -------------- one item in 5
7.C and MATLAB are languages



8.
systemC
| |
| synthesis-----mentorgraphics
|
-------simulation----modelsim
9.one APPROACH

download wimax phy code from hack site
its in systemC
use the above conversion model

10.TI tranceiver
http://docs.google.com/viewer?a=v&q=cache:kS_vtFHnmXoJ:focus.ti.com/general/docs/lit/getliterature.tsp%3FliteratureNumber%3Dslwu045%26fileType%3Dpdf+TI+dsp+kit+for+wimax+testing&hl=en&gl=in&pid=bl&srcid=ADGEESi3KhqXSbtILjhIRHJf6mn8I0jDyPRHOIuSIPSoIdjpXLJeBlb32MAy7bQF_jyfGaHDyxYsK7LGhxtPOjaUIupoVQ6W-VQ4ePIJhGLrvR_Uq_TTDpqFsaznpOszKccfk7GhmGbp&sig=AHIEtbR9No5uMxON8fylSqynDhJOqibhJw

arm cache and memory barrier

1.The main issue
compiler by default orders the instructions
optimizations may further reorder them
once the instructions get loaded into L1/L2 cache,then its rearranged by the core before
feeding into the cpu...here is where barrier comes into picture

A C code line should be converted to assembly,before we can decide whether we need to
use some kind of barrier or not

1.http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka14041.html
2.Memory barrier detailed
http://www.mjmwired.net/kernel/Documentation/memory-barriers.txt

MESI,MSI

MSI - modified,shared,invalid state of cache protocol

Cache Invalidation and Flushing
The VIRTUAL address is the argument for invalidation and flushing

wbinvd ---- writes cache back to memory and marks it empty
invd ---- just marks the cache as invalid without writing to ram

Excellent optimization tip
http://www.agner.org/optimize/

dma cache coherency

1.while a cpu has updated a buffer and about to give control and dma is about to start to device,
another cpu may update the same variable ... dma stales
2.after device dma's buffer, one cpu writes a variable to same buffer and another cpu reads it ...again its stale


1.cache invalidation and cache flushing are complementaries
2.Assume a copy of variable is read into cache
cpu modifies the cache value
but the ram value is old
if at this time device reads the variable(dma writes to device)
device sees incorrect value

3.Again a variable is reflected in cache
device updates the value in ram of variable
but cpu reads the stale value from cache

http://msdn.microsoft.com/en-us/library/ff545924(VS.85).aspx

===========================
1.above dma coherence simple scenario
2.cache line dma coherence scenario

scenario 2 explained
device writes to ram for a variable x
vaiable shares a cache line with another variable y
cpu modifies the variable y and flushes y
stale value of x is also flushed
it overwrites x in ram
later wrong value of x is read into cache and by cpu

another one
system is about to write x to device
another thread cpu modifies x
system will write old value